The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In addition, metal gate electrodes have been introduced as a replacement to polysilicon gate electrodes. Metal gate electrodes provide a number of advantages over polysilicon gate electrodes such as avoidance of the polysilicon depletion effect, work-function tuning by selection of appropriate gate metal(s), as well as other benefits. By way of example, a metal gate electrode fabrication process may include a metal layer deposition followed by a subsequent metal layer cut process (or metal gate cut process). The metal layer cut process sometimes forms a trench that not only dissects the metal gate, but also goes through an inter-layer dielectric (ILD) layer near the source/drain (S/D) features. A dielectric material may be subsequently filled into this trench. However, existing trench-filling material and method have some limitations. For example, the trench-filling material may have different etch selectivity than the ILD layer, which may sometimes cause hillocks in the S/D contact landing area. These hillocks may increase contact resistance of the S/D contact and reduce yield.
Thus, existing techniques have not proved entirely satisfactory in all respects.